Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Electronics For You

Icarus Verilog: Your First Step Into Digital Design

Learn how a free tool lets you build and test digital circuits on your computer and see how chips really work before making ...
Electronics Weekly

Using Verilog-A simulation in analogue design

A key part of any analogue design flow is having models of the components for simulation. Traditional Spice models of basic components such as transistors and capacitors written in C or C++ are ...
EDN

The pitfalls of mixing formal and simulation: Examples of the trouble

Driven by the need to objectively measure the progress of their verification efforts and the contributions of different verification techniques, IC designers have adopted coverage as a metric. However ...
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
Semiconductor Engineering

Shift-Left Low Power Verification With UPF Information Model

Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power ...
Business Insider

Metrics, R&D-Stage Startup Montana Announce Intention to MergeMetrics Simulator, Unique Montana Approach with System Verilog Processing Unit Bridge Gap between Simulation and ...

OTTAWA, June 25, 2018 (GLOBE NEWSWIRE) -- Metrics Technologies, the trailblazing cloud-based simulation and verification management solutions provider leveraging Google Cloud, and R&D-stage startup ...