EDN

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
EDN

Using SystemVerilog for functional verification

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...
Semiconductor Engineering

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs

Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA ...
Design-Reuse

Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization

MOUNTAIN VIEW, Calif., July 26, 2006--Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that it has donated a library of advanced SystemVerilog assertion ...
Design-Reuse

Case Study: Annotating OVL 2.0 with SVA Assertions

In this case study we attempt to annotate a subset of OVL 2.0 checkers using equivalent SVA properties. In doing so, we define the equivalence between checkers, or assertions, based on what input ...