EDN

Power tool taps clock gating

Claiming breakthrough technology in IC power optimization, Calypto Design Systems Inc. (Santa Clara, Calif.) this week will announce PowerPro CG, a tool that automatically adds clock-gating logic to ...
Business Wire

PCI Express Clock Jitter Measurement Tool from Silicon Labs Simplifies Timing Design

AUSTIN, Texas--(BUSINESS WIRE)--Silicon Labs (NASDAQ: SLAB) has introduced a free software tool that enables engineers to quickly and easily measure PCI Express® (PCIe®) clock jitter from an ...
EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
Electronics Weekly

Silicon Labs launches custom clock design tool

Silicon Labs’ new Clock Tree Expert tool enables embedded developers to generate sophisticated, streamlined clock tree block diagrams within minutes, simplifying system design, reducing bill of ...
Design-Reuse

SOC: Submicron Issues -> Integrated approach lets new tech in

Tools that integrate clock tree synthesis with logic synthesis, placement, route and interconnect extraction will have the power to maximize the potential of new process technologies in cell-based ...